The invention relates to a single chip microcomputer, and more particularly to an improvement in a throughput of a single chip microcomputer.
Single chip microcomputers, in which a central processing unit (a CPU), storage devices or memory devices and peripheral interfaces are integrated on a single semiconductor chip, are attractive because of low cost of manufacturing and high reliability, in addition to low power consumption. Such single chip microcomputers are thus widely used in various fields. Simplification of fabrication processes of single chip microcomputers brings the cost down and improves the reliability. One of the most important factors in performances of microcomputers such as the single chip microcomputers is the throughput which is the total ability thereof to process data in a specified time period. How to improve the throughput of microcomputers as much as possible is thus very important. The effective throughput of the single chip microcomputer is associated with interrupt processes which force the central processing unit (CPU) to stop temporarily a current execution of a program for a subsequent execution of an urgent process. When an interrupt request signal is generated, a program in a current operation by the CPU is interrupted. A state of the program at the point at which the execution of the program is interrupted is saved before subsequent execution of the interrupt servicing program, after the execution of which the original program is returned so that the original program's operation will be reinitiated at the point at which it was interrupted.
There exists a single chip microcomputer having a direct memory access feature in which a data transfer between memories and external devices is conducted independently from the CPU operation. Namely, blocked data are transferred between memories and external devices without passing through the CPU so that a high speed data transfer is implemented. Such data transfer is controlled by a direct memory access controller which forces the CPU to take on a hold state so the controller may take exclusive control of a system bus in order to conduct the direct access memory transfer.
In the conventional single chip microcomputers, when a hold request signal is generated during an execution by CPU of a program fetched from a read only memory (a ROM) in the single chip microcomputer, the current program operation by the CPU is continued. In contrast, if a hold request signal is also generated during an execution by the CPU of a program fetched from an external storage device outside the chip, the current program operation by the CPU is interrupted. Since the interrupt request signal for urgent processing is generated during such hold state of the CPU, it is impossible to allow the CPU to execute the interrupt servicing program until the hold state of the CPU is released. It is no doubt apparent that such impossibility of interrupt servicing program's operation provides a restriction to the throughput of the single chip microcomputer. The above matters will be described more closely and concretely with reference to FIG. 1 which is illustrative of a hardware construction of a typical one of the conventional single chip microcomputers.
In FIG. 1, the single chip microcomputer 500 includes an interrupt controller 1, a central processing unit (a CPU) 2, an external interface 3, a random access memory (a RAM) 4, a read only memory (a ROM) 5, a peripheral device 6 and an internal bus 7. The interrupt controller 1 is connected through a bidirectional internal bus 27 to the internal bus 7. The central processing unit (CPU) 2 is also connected through a bidirectional internal bus 26 to the internal bus 7. The external interface 3, the random access memory (RAM) 4, and the peripheral device 6 are respectively connected through bidirectional internal buses 25, 29 and 30 to the internal bus 7. The read only memory (ROM) 5 is also connected to the internal bus 2 but through an unidirectional internal bus 28.
The interrupt controller 1 is connected to an interrupt request signal line 11. The central processing unit (CPU) 2 has an address register (2-1) which stores address of orders to fetch. The central processing unit (CPU) 2 is connected to a hold request signal line 12. The interrupt controller 1 and the central processing unit (CPU) 2 are connected to each other through both an interrupt acknowledge signal line 16 and an interrupt request signal line 17. The central processing unit (CPU) 2 is also connected to a hold acknowledge signal line 13 connecting to both an external device and the external interface 3. The external interface 3 is connected to a read strobe signal line 14, a write strobe signal line 15, an internal data bus 23 and an internal address bus 24. The internal data bus 23 is a bidirectional interface bus, but the internal address bus 24 is but a unidirectional interface bus. The internal address bus 24 transmits addresses from the external interface 3 to an external memory device for access to the external memory device, in which the address has been supplied from the internal bus 7 through the internal bus 25 to the external interface 3. The internal data bus 23 transmits data from the external interface 3 to the external memory device for access to the external memory device, in which the data has been supplied from the internal bus 7 through the internal bus 25 to the external interface 3. The random access memory 4 is a storage device from which data is read from or written to. The read only memory (ROM) 5 is a storage device which permanently stores user programs and fixed data. The central processing unit (CPU) 2 executes operations of programs stored in the read only memory (ROM) 5 or in a storage device. The peripheral device 6 may comprise a port which communicates with external devices through an external terminal 6-1. The peripheral device 6 receives data transmitted through the external terminal 6-1 from the external device, and then supplies the data to the internal bus 7 through the bus 30. The internal bus 7 is an interface bus which conducts a time division transmission of address and data.
The operation of the conventional single chip microcomputer 500 will subsequently be described. When a hold request is generated in the external device, a hold request signal S12 takes a 1 state. The hold request signal S12 is transmitted on the hold request signal line 12 to the central processing unit (CPU) 2. The central processing unit (CPU) 2 receives the hold request signal S12 and then generates and delivers a hold acknowledge signal S13 which is transmitted on the hold acknowledge signal line 13 to both the external device and the external interface 3. The central processing unit (CPU) 2 takes the following different two states according to the address stored in the address register in the central processing unit (CPU) 2, and thus depending upon what the central processing unit (CPU) 2 specifies as objects of its operation according to values stored in the address register 2-1.
A first case is that according to the value stored in the address register 2-1 the central processing unit 2 specifies the read only memory (ROM) 5 for a subsequent program operation or data processing. As described above, the central processing unit (CPU) 2 receives the hold request signal S12 transmitted on the hold request signal line 12, and then generates and delivers the hold acknowledge signal S13 to both the external device and the external interface 3 through the hold acknowledge signal line 13. The central processing unit (CPU) 2 subsequently continues the current operation of data processing. Namely, in this case, the central processing unit (CPU) 2 does not takes any hold state. In addition, the external interface 3 receives the hold acknowledge signal S13 transmitted from the central processing unit (CPU) 2 and then makes all of its outputs take on high impedance states. Namely, at this time, the read strobe signal line 14, the write strobe signal line 15, the address bus 23 and the data bus 24 take the high impedance state, resulting in no output of a read strobe signal S14 on the read nor output of a write strobe signal S15 on the write strobe signal line 15, in addition to no output of a data signal on the data bus 23 nor an input of an address signal S24 on the address bus 24. In the meantime of the above process, there is a possibility of a generation of an interrupt request outside the microcomputer chip. When an interrupt request signal S11 is generated, the interrupt request signal line 11 to the interrupt controller 1. The interrupt controller 11 receives the interrupt request signal S11, and then generates and delivers an interrupt request signal S17 which is transmitted though the interrupt request signal line 17 to the central processing unit (CPU) 2. After that, the central processing unit (CPU) 2 receives the interrupt request signal 17 and thus delivers an interrupt acknowledge signal S16 back to the interrupt controller 1 through the interrupt acknowledge signal line 16. The interrupt controller 1 synchronizes with the interrupt acknowledge signal S16 and generates a vectored interrupt which is subsequently transmitted through the bus 27 to the bus 7. The internal bus 7 transmits the vectored interrupt through the bus 26 to the central processing unit (CPU) 2. The central processing unit (CPU) 2 receives the vectored interrupt and then executes an interrupt program according to the vectored interrupt. After than, the data processing or the program operation by the central processing unit (CPU) 2 continues at the point at which the data processing or the program operation was interrupted.
Subsequently, when the hold request signal S12 takes a 0 state and thus the hold request is released, the central processing unit (CPU) 2 continues executing the current program operation or the current data processing. The high impedance state of the external interface 3 is released. The hold acknowledge signal S13 takes a 0 state.
From the above description, in the first case in which the central processing unit (CPU) 2 processes the data or the program fetched from the read only memory (ROM) 5, there is no problem with a lowering of the throughput of the microcomputer 500.
Such problem with lowering the throughput of the single chip microcomputer 500, however, appears in the second case in which the central processing unit (CPU) 2 processes data or a program which has been stored in an external storage device. The problem will be cleared by describing the operation of the microcomputer 500 in the second case, also with reference to FIG. 1.
The central processing unit specifies an external storage device according to the address stored in the address register 2-1, and subsequently fetches data or programs stored in the external storage device for an execution of data processing or program operation. The central processing unit (CPU) 2 receives the hold request signal S12 transmitted on the hold request signal line 12, and then generates and delivers the hold acknowledge signal S13 to both the external device and the external interface 3 through the hold acknowledge signal line 13. The central processing unit (CPU) 2 subsequently stops or interrupts the current program operation or data processing. Namely, in this case, the central processing unit (CPU) 2 takes a hold state and thus is not operational. Hence, any order or request is not acceptable to the central processing unit 2 taking the hold state. In addition, the external interface 3 receives the hold acknowledge signal S13 transmitted from the central processing unit (CPU) 2 and then makes its all outputs take on high impedance states. In the meantime of the above process, there is a possibility of a generation of an interrupt request outside the microcomputer chip. When an interrupt request signal S11 is generated, the interrupt request signal S11 is transmitted through the interrupt request signal line 11 to the interrupt controller 1. The interrupt controller 1 receives the interrupt request signal S11, and then generates and delivers an interrupt request signal S17 which is subsequently transmitted through the interrupt request signal line 17 to the central processing unit (CPU) 2 taking the hold state or being not operational. The central processing unit (CPU) 2 at such the state is unable to receive or accept the interrupt request signal 17. Namely, the interrupt request is rejected by the central processing unit (CPU) 2, because it has taken on the hold state, resulting in no execution of the interrupt processing, even if the interrupt request is urgent and prompt interrupt processing is very important. That is why the interrupt processing is forced to wait until the central processing unit (CPU) 2 is released from the hold state.
When the hold request signal S12 takes a 0 state and thus the hold request is released, the central processing unit (CPU) 2 is released from the hold state. So the central processing unit (CPU) 2 becomes operational and thus being able to receive or accept the interrupt request signal S17, and then delivers an interrupt acknowledge signal S16 back to the interrupt controller 1 through the interrupt acknowledge signal line 16. The interrupt controller 1 synchronizes with the interrupt acknowledge signal S16 and generates a vectored interrupt which is subsequently transmitted through the bus 27 to the bus 7. The internal bus 7 transmits the vectored interrupt through the bus 26 to the central processing unit (CPU) 2. The central processing unit (CPU) 2 receives the vectored interrupt and then executes an interrupt process according to the vectored interrupt. After processing the interrupt routine, the central processing unit (CPU) 2 continues executing the program operation or the data processing at the point at which it was interrupted by appearance of the hold request.
From the above descriptions, in the second case that the central processing unit (CPU) 2 processes the data or the program fetched from an external storage device, there is the problem of a lowering of the throughput of the microcomputer 500, because the interrupt process is forced to wait until the hold state of the central processing unit (CPU) 2 is released.
As the performance speed of central processing units is improved, the disadvantage caused by many interrupt requests that are unable to be processed by the central processing unit at the hold state is considerable. It seems that in the case of using a direct memory access transfer, the time during which the central processing unit takes on the hold state is approximately several hundreds microseconds. If it were possible for the central processing unit to execute interrupt processing during a hold state continuing for so long time, several hundreds of interrupt requests would be expected to be processed.
It is therefore desirable to develop a novel microcomputer which allows a central processing unit to execute interrupt processes not only when the central processing unit does not take a hold state but also when the central processing unit takes the hold state to improve the throughput of the microcomputer.